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HT46RB50 A/D Type USB 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note
Features
* Operating voltage: * 6-level subroutine nesting * 8 channels 10-bit resolution A/D converter * 2-channel 8-bit PWM output shared with two I/O lines * SIO (synchronous serial I/O) function * Supports Interrupt, Control, Bulk transfer * USB 1.1 full speed function compatible * 4 endpoints supported (endpoint 0 included) * Total FIFO size is 88 byte (8, 8, 8, 64 for EP0~EP3) * Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * Low voltage reset function * 28-pin SOP/SKDIP, 48-pin SSOP package
fSYS=6MHz: 2.2V~5.5V fSYS=12MHz: 2.7V~5.5V
* 38 bidirectional I/O lines (max.) * 1 interrupt input shared with an I/O line * One 16-bit programmable timer/event counter with
overflow interrupt
* One 8-bit programmable timer/event counter with
overflow interrupt and 7 stage prescaler
* Only crystal oscillator (6MHz or 12MHz) * Watchdog Timer * 409615 program memory * 1928 data memory RAM * HALT function and wake-up feature reduce power
consumption
* Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
General Description
This device is an 8-bit high performance RISC architecture microcontroller designed for USB product applications. It is particularly suitable for use in products such as USB and/or SPI touch-panels, USB and/or SPI touch-pads, PS II joysticks, XBOX joysticks, USB Mice keyboards and joystick. A HALT feature is included to reduce power consumption.
Rev. 1.20
1
November 1, 2006
HT46RB50
Block Diagram
USBD+ USBDV33O TM R0C U S B 1 .1 F u ll S p e e d M U X TM R0 P r e s c a le r P C 1 /T M R 0 fS
YS
In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C
TM R1C M TM R1
U X
fS
YS
/4
P C 2 /T M R 1
E N /D IS W DTS In s tr u c tio n R e g is te r MP M U X DATA M e m o ry W D T P r e s c a le r WDT M U X fS
YS
/4
W DT OSC
PAC In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PA
P o rt A
PA0~PA7
PBC STATUS PB A /D
P o rt B C o n v e rte r
P B 0 /A N 0 ~ P B 7 /A N 7
PCC OSC2 OSC1 RES VDD VSS AVDD AVSS ACC PC PDC PD PW M PEC PE S e r ia l In te rfa c e
P o rt C
P C 0 /IN T PC 3~PC 7
P o rt D
P D 0 /P W M 0 ~ P D 1 /P W M 1 , PD 2~PD 7
P o rt E
PE PE PE PE PE
4~P 0 /S 1 /C 2 /S 3 /S
E5 CS LK DI DO
Rev. 1.20
2
November 1, 2006
HT46RB50
Pin Assignment
PA3 PA2 PA1 PA0 PD3 PD2 P D 1 /P W M 1 P D 0 /P W M 0 P B 7 /A N 7 P B 6 /A N 6 PA3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PA2 PA1 PA0 P D 1 /P W M 1 P D 0 /P W M 0 P B 5 /A N 5 P B 4 /A N 4 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 P E 3 /S D O P E 2 /S D I 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PA4 PA5 PA6 PA7 RES V D D /A V D D V S S /A V S S OSC1 OSC2 V33O UDP UDN P C 0 /IN T P E 1 /C L K P B 5 /A N 5 P B 4 /A N 4 PC7 PC6 PC5 PC4 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 P E 3 /S D O P E 2 /S D I P E 1 /C L K P E 0 /S C S 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PA4 PA5 PA6 PA7 PD4 PD5 PD6 PD7 RES AVDD VDD AVSS VSS OSC1 OSC2 PE4 PE5 V33O UDP UDN P C 0 /IN T P C 1 /T M R 0 P C 2 /T M R 1 PC3
H T46R B 50 2 8 S O P -A /S K D IP -A
H T46R B 50 4 8 S S O P -A
Pin Description
Pin Name I/O Options Pull-high (bit option) Wake-up (bit option) Pull-high (bit option) Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is controlled by PAC (PA control register, bit option). Pull-high resistor options: PA0~PA7, bit option, wake-up options: PA0~PA7. Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: bit option). The PB can be used as analog input of the analog to digital converter. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PC0, PC1 PC2 are pin-shared with INT, TMR0 or TMR1, respectively. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PD0/PD1 are pin-shared with PWM0/PWM1 (dependent on PWM options). Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PE0 is pin-shared with SCS. SCS is a chip select pin of the Serial interface, Master mode is output, Slave mode is input. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PE1 is pin-shared with CLK. CLK is a Serial interface serial clock input/output (Initial is input).
PA0~PA7
I/O
PB0/AN0~ PB7/AN7 PC0/INT PC1/TMR0 PC2/TMR1 PC3~PC7 PD0/PWM0~ PD1/PWM1 PD2~PD7
I/O
I/O
Pull-high (nibble option)
I/O
Pull-high (nibble option) I/O or PWM
PE0/SCS
I/O
Pull-high (nibble option)
PE1/CLK
I/O
Pull-high (nibble option)
Rev. 1.20
3
November 1, 2006
HT46RB50
Pin Name I/O Options Pull-high (nibble option) Description Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PE2 is pin-shared with SDI. SDI is Serial interface serial input. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). The PE3 is pin-shared with SDO. SDO is a Serial interface serial output. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). Schmitt trigger reset input, active low Negative power supply, ground ADC negative power supply, ground Positive power supply ADC positive power supply, AVDD should be externally connected to VDD. OSC1 and OSC2 are connected to a 6MHz or 12MHz Crystal/resonator (determined by software instructions) for the internal system clock. 3.3V regulator output. UDP is USBD+ line USB function is controlled by software control register. UDN is USBD- line USB function is controlled by software control register.
PE2/SDI
I/O
PE3/SDO
I/O
Pull-high (nibble option)
PE4~PE5 RES VSS AVSS VDD AVDD OSC1 OSC2 V33O UDP UDN
I/O I 3/4 3/4 3/4 3/4 I O O I/O I/O
Pull-high (nibble option) 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 5V 3V 5V 3V 5V 3V 5V Conditions fSYS=6MHz fSYS=12MHz No load, fSYS=6MHz No load, fSYS=12MHz No load, system HALT, USB suspended No load, system HALT, USB suspended Min. 2.2 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 6.5 3.6 7.5 3/4 3/4 3/4 3/4 Max. 5.5 5.5 12 10 16 5 10 1 2
Ta=25C Unit V V mA mA mA mA mA mA mA
VDD IDD1 IDD2
Operating Voltage Operating Current (6MHz Crystal) Operating Current (12MHz Crystal)
ISTB1
Standby Current (WDT Enabled)
ISTB2
Standby Current (WDT Disabled)
Rev. 1.20
4
November 1, 2006
HT46RB50
Symbol Parameter Test Conditions VDD 5V 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V 5V 3/4 5V 3/4 Conditions No load, system HALT, USB transceiver and 3.3V regulator On 3/4 3/4 3/4 3/4 VOL=0.1VDD Min. Typ. Max. Unit
ISTB3 VIL1 VIH1 VIL2 VIH2 IOL
Standby Current (WDT Disabled) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current
3/4 0 0.7VDD 0 0.9VDD 4 10 -2 -5 20 10 2.7 3 3/4
150 3/4 3/4 3/4 3/4 8 20 -4 -10 60 30 3 3.3 0.5
200 0.3VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 100 50 3.3 3.6 1
mA V V V V mA mA mA mA kW kW V V LSB
IOH
I/O Port Source Current
VOH=0.9VDD 3/4 Option 3.0V IV33O=-5mA 3/4
RPH VLVR VV33O EAD
Pull-high Resistance Low Voltage Reset Voltage 3.3V Regulator Output A/D Conversion Error
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3/4 3V 5V 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 Min. 400 400 0 0 45 32 1 3/4 1 1 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 90 65 3/4 1024 3/4 3/4 76 32 Max. 6000 12000 6000 12000 180 130 3/4 3/4 3/4 3/4 3/4 3/4
Ta=25C Unit kHz kHz kHz kHz ms ms ms *tSYS ms ms tAD tAD
fSYS
System Clock
fTIMER
Timer I/P Frequency (TMR0/TMR1)
tWDTOSC tRES tSST tINT tAD tADC tADCS
Watchdog Oscillator Period External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time
Note: *tSYS=1/fSYS
Rev. 1.20
5
November 1, 2006
HT46RB50
Functional Description
Execution Flow The system clock is derived from a crystal. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 12 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manages the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction, otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k PC
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Mode Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow USB Interrupt A/D Converter Interrupt Serial Interface Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
Rev. 1.20
6
November 1, 2006
HT46RB50
Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits which are addressed by the Program Counter and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H * Location 00CH
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
Location 000H is reserved for program initialization. After a chip reset, the program always begins execution at this location.
* Location 004H
Location 010H is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
Location 004H is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Location 014H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and the stack is not full, the program begins execution at location 014H.
* Location 018H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
000H 004H 008H 00C H 010H 014H 018H A /D D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e U S B In te r r u p t S u b r o u tin e C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
Location 018H is reserved when 8 bits data have been received or transmitted successfully from serial interface, and the related interrupts are enabled, and the stack is not full, the program begins execution at location 018H.
* Table location
S e r ia l In te r fa c e In te r r u p t S u b r o u tin e
n00H nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon users requirements. Stack Register - STACK
FFFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 B its N o te : n ra n g e s fro m 0 to F
Program Memory
This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. Table Location
Instruction *11 TABRDC [m] TABRDL [m] P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.20 7 P11~P8: Current program counter bits
November 1, 2006
HT46RB50
At a subroutine call or an interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of the subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure more easily. If the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 2388 bits, and is divided into two functional groups, namely; special function registers (468 bits) and general purpose data memory (1928 bits) most of which are readable/writeable, although some are read only. The unused space before 40H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing into it, indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. Accumulator - ACC The accumulator is closely related to ALU operations. It is also mapped to location 05H of the RAM and capable of operating with immediate data. The data movement between two data memory locations must pass through the accumulator.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3FH 40H SBCR SBDR ADRL ADRH ADCR ACSR PW M0 PW M1 USC USR UCC AW R STALL S IE S M IS C S E T IO F IF O 0 F IF O 1 F IF O 2 F IF O 3 IN T C 1 S p e c ia l P u r p o s e D a ta M e m o ry TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PE PEC STATUS IN T C 0 ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
FFH
G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s )
:U nused R e a d a s "0 0 "
RAM Mapping
Rev. 1.20
8
November 1, 2006
HT46RB50
Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
Interrupts This device provides external interrupts (INT pin interrupt, A/D Converter interrupt, Serial Interface interrupt) and internal timer/event counter interrupts. The Interrupt Control Register0 (INTC0;0BH) and interrupt control register1 (INTC1:1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts can are triggered by a falling edge transition of INT), and the related interrupt request flag (EIF; bit4 of the INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active (INT pin), a subroutine call at location 04H occurs. The interrupt flag (EIF) and EMI bits are all cleared to disable other maskable interrupts. Function
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.
Bit No. 0
Label C
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
Rev. 1.20
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November 1, 2006
HT46RB50
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of the INTC0), caused by a Timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of the INTC0), caused by a Timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC1) will be set.
* The access of the corresponding USB FIFO from PC * The USB suspend signal from the PC * The USB resume signal from the PC * USB Reset signal
rupt is triggered. So user can easily determine which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT46RB50 receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT46RB50 is set and a USB interrupt is also triggered. Also when the HT46RB50 receives a Resume signal from the Host PC, the resume line (bit3 of the ) of the HT46RB50 is set and a USB interrupt is triggered. Whenever a USB reset signal is detected, a USB interrupt is triggered. The A/D converter interrupt is controlled by setting the A/D interrupt control bit (EADI; bit 1 of the INTC1). When the interrupt is enabled, the stack is not full and the A/D conversion is finished, a subroutine call to location 14H will occur. The related interrupt request flag ADF (bit5 of the INTC1) will be reset and the EMI bit cleared to disable further interrupts. The serial interface interrupt is indicated by the interrupt flag (SIF; bit 6 of the INTC1), that is caused by a reception or a complete transmission of an 8-bit data between the HT46RB50 and an external device. The serial interface interrupt is controlled by setting the Serial interface interrupt control bit (ESII ; bit 2 of the INTC1). After the interrupt is enabled (by setting SBEN; bit 4 of the SBCR), and the stack is not full and the SIF is set, a subroutine call to location 18H occurs.
When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 10H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When PC Host access the FIFO of the HT46RB50, the corresponding request bit of USR is set, and a USB interBit No. 0 1 2 3 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4
Function Controls the master (global) interrupt (1= enable; 0= disable) Controls the external interrupt (1= enable; 0= disable) Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable) Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable) External interrupt request flag (1= active; 0= inactive) Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC0 (0BH) Register
Bit No. 0 1 2 3, 7 4 5 6
Label EUI EADI ESII 3/4 USBF ADF SIF
Function Control the USB interrupt (1= enable; 0= disable) Control the A/D converter interrupt (1= enable; 0=disable) Control Serial interface interrupt (1= enable; 0= disable) Unused bit, read as 0 USB interrupt request flag (1= active; 0= inactive) A/D converter request flag (1= active; 0= inactive) Serial interface interrupt request flag (1= active; 0= inactive) INTC1 (1EH) Register
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During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow USB Interrupt A/D Converter Interrupt Serial Interface Interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters a power down mode and the system clock is stopped, but the WDT oscillator still works. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) determined by options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by options. If the watchdog timer is disabled, all executions related to the WDT results in no operation. Once an internal WDT oscillator (RC oscillator with a period of 65ms, normally at 5V) is selected, it is divided by 212~215 (by option to get the WDT time-out period). The WDT time-out minimum period is 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection from the WDT option, longer time-out periods can be realized. If the WDT time-out is selected as 215, the maximum time-out period is divided by 215~216 which about 2.3s~4.7s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset and only the Program Counter and SP are reset to zero. To clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip due to time-out.
It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There is an oscillator circuit in the microcontroller.
OSC1
OSC2 C r y s ta l O s c illa to r
System Oscillator This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an external signal to conserve power. A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
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S y s te m C lo c k /4 ROM C ode o p tio n fW
DT
D iv id e r
fW
DT
/2
8
W D T P r e s c a le r
W DT OSC (1 2 k H z )
M a s k O p tio n W D T C le a r
CK R
T
CK R
T
T im e - o fs /2 1 5 ~ fs /2 1 4 ~ fs /2 1 3 ~ fs /2 1 2 ~
utR eset fs /2 1 6 fs /2 1 5 fs /2 1 4 fs /2 1 3
Watchdog Timer Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator is turned off but the WDT oscil-
lator keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and registers remain
period) to resume normal operation. In other words, a dummy period is inserted after wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset may occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
unchanged.
* The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the real time clock).
* All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
The system can quit the HALT mode in many ways, by an external reset, an interrupt, an external falling edge signal on Port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag is cleared by a system power-up or by executing the CLR WDT instruction and is set when executing the HALT instruction. On the other hand, the TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP; and leaves the others in their original status. The Port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in Port A can be independently selected to wake-up the device by option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the interrupt is enabled and the stack is not full, a regular interrupt response takes place. When an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. If a wake-up event occurs, it takes 1024 fSYS (system clock
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the Program Counter and Stack Pointer, leaving the other circuits in their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up at HALT WDT time-out during normal operation WDT wake-up at HALT
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up.
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V
DD
VDD
0 .0 1 m F * 100kW RES 10kW 0 .1 m F *
RES S S T T im e - o u t C h ip R eset
tS
ST
+ tO
PD
Reset Timing Chart
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
Awaking from the HALT state or system power up, an SST delay is added. An extra SST delay is added during power up period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset status are shown below. Program Counter 000H Disable Cleared Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
HALT W DT
RES
W DT T im e - o u t R eset
W a rm
R eset
Interrupt Prescaler, Divider
E x te rn a l C o ld R eset
WDT Timer/event Counter Input/output Ports Stack Pointer
OSC1
SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
Reset Configuration
The registers states are summarized in the following table. Reset (Power On) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxxx xxxx --00 xxxx -000 0000 -000 -000 1111 1111 WDT Time-out (Normal Operation) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 -000 -000 1111 1111 RES Reset (Normal Operation) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 -000 -000 1111 1111 RES Reset (HALT) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 -000 -000 1111 1111 WDT Time-out (HALT)* uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu -uuu -uuu uuuu uuuu USB Reset (Normal) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 -000 -000 1111 1111 USB Reset (HALT) xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 -000 -000 1111 1111
Register
TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC0 INTC1 PA
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Reset (Power On) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 ---- 1110 0xx- -000 ---- 1110 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1-00 0000 --00 0000 -000 0000 0100 0000 xx-- ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx WDT Time-out (Normal Operation) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- uuuu uxx- -uuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu --uu uuuu -uuu uuuu uuuu uuuu xx-- ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx RES Reset (Normal Operation) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 ---- 1110 0xx- -000 ---- 1110 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1-00 0000 --00 0000 -000 0000 0100 0000 xx-- ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx RES Reset (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 ---- 1110 0xx- -000 ---- 1110 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1-00 0000 --00 0000 -000 0000 0100 0000 xx-- ---xxxx xxxx 0100 0000 1--- --00 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu uxx- -uuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu --uu uuuu -uuu uuuu uuuu uuuu uu-- ---uuuu uuuu uuuu uuuu u--- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset (Normal) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 ---- 1110 000- -000 ---- 1110 0000 0000 0000 0000 0000 0000 0000 0000 u-00 0100 --00 0000 -uu0 u000 0100 0000 xx-- ---xxxx xxxx 0100 0000 1--- --00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 ---- 1110 000- -000 ---- 1110 0000 0000 0000 0000 0000 0000 0000 0000 u-00 0100 --00 0000 -uu0 u000 0100 0000 xx-- ---xxxx xxxx 0100 0000 1--- --00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Register
PAC PB PBC PC PCC PD PDC PE PEC AWR STALL MISC SETIO FIFO0 FIFO1 FIFO2 FIFO3 USC USR UCC SIES ADRL ADRH ADCR ACSR PWM0 PWM1 SBCR SBDR Note:
* stands for warm reset u stands for unchanged x stands for unknown
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Timer/Event Counter Two Timer/Event Counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains a 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. There are five registers related to the Timer/Event Counter 0; TMR0 (0DH), TMR0C (0EH) and the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). For 16bits timer to Write data to TMR1L will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L registers. The Timer/Event Counter 1 preload register is changed by each writing TMR1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFFFH(for 16 bits timer is FFFFH, bit 8 bits timer will be FFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of the INTC0, T1F; bit 6 of the INTC0).
PW M (6 + 2 ) o r (7 + 1 ) C o m p a re fS
YS
T o P D 0 /P D 1 C ir c u it
8 - s ta g e P r e s c a le r 8 -1 M U X T0D 2~T0D 0 TM R0 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r (T M R 0 ) O v e r flo w to In te rru p t f IN
T
D a ta B u s TM 1 TM 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 0
fS
YS
/4
f IN
T
D a ta B u s TM 1 TM 0 1 6 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
TM R1 TE TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 - B it T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L )
O v e r flo w to In te rru p t
Timer/Event Counter 1
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In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the T0E/T1E bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (T0ON: bit 4 of the TMR0C; T10N: bit 4 of the TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. Bit No. Label In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The timer prescaler is also used as the PWM counter.
Function Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR active edge of the timer/ event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode, T0M1, T0M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register
0 1 2
T0PSC0 T0PSC1 T0PSC2
3 4 5
T0E T0ON 3/4
6 7
T0M0 T0M1
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Bit No. 0~2, 5 3 4 Label 3/4 T1E T1ON Unused bit, read as 0 Defines the TMR active edge of the timer/ event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disable; 1=enable) Defines the operating mode, T1M1, T1M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Input/Output Ports There are 38 bidirectional input/output lines in the microcontroller, labeled from PA to PE, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [1A] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1A). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source also depends on the control register. If the control register bit is 1 the input will read the pad state. If the control register bit is 0 the contents of the latches will move to the internal bus. The latter is possible in the Read-modifywrite instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H and 1BH. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H or 1AH ) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator.
V C o n tr o l B it Q D CK S Q PU
DD
Function
6 7
T1M0 T1M1
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q M U X
W r ite D a ta R e g is te r
PA0 PB0 PC0 PC1 PC2 PC3 PD0 PD2 PE0 PE1 PE2 PE3 PE4
~P /A /IN /T /T ~P /P ~P /S /C /S /S ~P
A7 N 0 ~ P B 7 /A N 7 T MR0 MR1 C7 W M 0 ~ P D 1 /P W M 1 D7 CS LK DI DO E5
PD 0~PD 3 PW M 0~PW M 3 M U X R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly )
M a s k O p tio n
M a s k O p tio n
IN T fo r P C 0 T M R 0 fo r P C 1 T M R 1 fo r P C 2
Input/Output Ports
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Each line of Port A has the capability of waking-up the device. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Pulse Width Modulator - PWM The microcontroller provides 2 channels (6+2)/(7+1) (depending on options) bits PWM output shared with PD0/PD1. The data register of the PWM channels are denoted as PWM0 (34H) and PWM1 (35H). The frequency source of the PWM counter comes from fSYS. There are four 8-bit PWM registers. The waveforms of the PWM outputs are as shown. Once the PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1=0), writing a 1 to PD0/PD1 data register will enable the PWM output function and writing a 0 will force the PD0/PD1 to remain at 0.
fS
YS
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. Group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) i/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
(6+2) PWM Mode
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS
YS YS
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
M o d u la tio n c y c le 1
M o d u la tio n c y c le 0
(7+1) PWM Mode
Rev. 1.20
18
November 1, 2006
HT46RB50
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. Group 2 is denoted by AC which is the value of PWM.0. In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter Modulation cycle i (i=0~1) AC (0~1) iThe modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode PWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256
Selects the A/D converter clock source 00= system clock/2 ADCS0 01= system clock/8 ADCS1 10= system clock/32 11= Undefined 3/4 TEST Unused bit, read as 0 For test mode used only ACSR (33H) Register
2~6 7
Bit No. Label 0 1 2 3 4 5 ACS0 ACS1 ACS2 PCR0 PCR1 PCR2
Function Defines the analog channel select Defines the Port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption Indicates end of A/D conversion. (0= end of A/D conversion) Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation.
6
EOCB
7
Starts the A/D conversion. 0(R)1(R)0= Start START 0(R)1= Reset A/D converter and set EOCB to 1. ADCR (32H) Register
November 1, 2006
HT46RB50
ACS2 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRL ADRH Note: D1 D9 D0 D8 3/4 D7 3/4 D6 3/4 D5 3/4 D4 3/4 D3 3/4 D2
D0~D9 is A/D conversion result data bit LSB~MSB.
Analog Input Channel Selection
PCR2 0 0 0 0 1 1 1 1
PCR1 0 0 1 1 0 0 1 1
PCR0 0 1 0 1 0 1 0 1
7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7
6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6
5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5
4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4
3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3
2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2
1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1
0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0
Port B Configuration
M in im u m START
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
EOCB PC R2~ PCR0
A /D tA 000B
DCS
s a m p lin g tim e 100B
A /D tA
DCS
s a m p lin g tim e
A /D tA
DCS
s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
100B
101B
AC S2~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D tA D tA
CS
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
d o n 't c a r e
E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e
tA D C c o n v e r s io n tim e
YS
A /D
tA D C c o n v e r s io n tim e
A /D
DC
c lo c k m u s t b e fS = 3 2 tA D = 7 6 tA D
YS
/2 , fS
/8 o r fS
YS
/3 2
A/D Conversion Timing
Rev. 1.20
20
November 1, 2006
HT46RB50
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRH ; read conversion result high byte value from the ADRH register mov adrh_buffer,a ; save result to user defined memory mov a,ADRL ; read conversion result low byte value from the ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp Start_conversion ; start next A/D conversion Example: using Interrupt Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : :
; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt
; save ACC to user defined memory ; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D
Rev. 1.20
21
November 1, 2006
HT46RB50
EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti
; restore STATUS from user defined memory ; restore ACC from user defined memory
Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage range (0.9V~VLVR) has to be main-
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .0 V 2 .2 V
LVR
tained for over 1ms, otherwise, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the external RES
0 .9 V
signal to perform a chip reset. Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before resuming normal operation. *2: Low voltage state has to be maintained in its original state for over 1ms, then after 1ms delay, the device enters the reset mode.
Rev. 1.20
22
November 1, 2006
HT46RB50
Serial Interface Serial interface function has four basic signals included. They are SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Note: SCS can be named SCS in the design note.
SCS
C LK
SDI
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D7 SBCR D EFAU LT SBDR D EFAU LT U CKS 0 D7
D6 M1 1 D6 U
D5 M0 1 D5 U
D4 SBEN 0 D4 U
D3 M LS 0 D3 U
D2 CSEN 0 D2 U
D1 W COL 0 D1 U
D0 TRF 0 D0 U SBCR : S E R IA L B U S
C O N T R O L R E G IS T E R SBDR : S E R IA L B U S
D A T A R E G IS T E R
N o te : "U " m e a n s u n c h a n g e d .
Two registers (SBCR and SBDR) unique to serial interface provide control, status, and data storage.
* SBCR: Serial bus control register
Disable: SCK (SCK), SDI, SDO, SCS floating Bit3 (MLS) (R) MSB or LSB (1/0) shift first control bit Bit2 (CSEN) (R) serial bus selection signal enable/disable (SCS), when CSEN=0, SCSB is floating. Bit1 (WCOL) (R) this bit is set to 1 if data is written to SBDR (TXRX buffer) when data is transferred, writing will be ignored if data is written to SBDR (TXRX buffer) when data is transferred. Bit0 (TRF) (R) data transferred or data received used to generate an interrupt. Note: data receiving is still working when the MCU enters HALT mode.
Bit7 (CKS) clock source selection: fSIO=fSYS/4, select as 0 Bit6 (M1), Bit5 (M0) master/slave mode and baud rate selection M1, M0: 00 (R) MASTER MODE, BAUD RATE= fSIO 01 (R) MASTER MODE, BAUD RATE= fSIO/4 10 (R) MASTER MODE, BAUD RATE= fSIO/16 11 (R) SLAVE MODE
* Bit4 (SBEN) (R) serial bus enable/disable (1/0)
Enable: (SCS dependent on CSEN bit) Disable (R) enable: SCK, SDI, SDO, SCS= 0 (SCKB= 0) and waiting for writing data to SBDR (TXRX buffer) Master mode: write data to SBDR (TXRX buffer) start transmission/reception automatically Master mode: when data has been transferred, set TRF Slave mode: when an SCK (and SCS dependent on CSEN) is received, data in TXRX buffer is shifted-out and data on SDI is shifted-in.
* SBDR: Serial bus data register
Data written to SBDR (R) write data to TXRX buffer only Data read from SBDR (R) read from SBDR only Operating Mode description: Master transmitter: clock sending and data I/O started by writing SBDR Master clock sending started by writing SBDR Slave transmitter: data I/O started by clock received Slave receiver: data I/O started by clock received
Rev. 1.20
23
November 1, 2006
HT46RB50
Clock polarity= rising (CLK) or falling (CLK): 1 or 0 (mask option) Modes 1. 2. 3. 4. Master 5. 6. 7. 8. 9. 1. 2. 3. 4. Operations Select CKS and select M1, M0 = 00,01,10 Select CSEN, MLS (the same as the slave) Set SBEN Writing data to SBDR (R) data is stored in TXRX buffer (R) output CLK (and SCS) signals (R) go to step 5 (R) (SIO internal operation (R) data stored in TXRX buffer, and SDI data is shifted into TXRX buffer (R) data transferred, data in TXRX buffer is latched into SBDR) Check WCOL; WCOL= 1 (R) clear WCOL and go to step 4; WCOL= 0 (R) go to step 6 Check TRF or waiting for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4 CKS dont care and select M1, M0= 11 Select CSEN, MLS (the same as the master) Set SBEN Writing data to SBDR (R) data is stored in TXRX buffer (R) waiting for master clock signal (and SCS): CLK (R) go to step 5 (R) (SIO internal operations (R) CLK (SCS) received (R) output data in TXRX buffer and SDI data is shifted into TXRX buffer (R) data transferred, data in TXRX buffer is latched into SBDR) Check WCOL; WCOL= 1 (R) clear WCOL, go to step 4; WCOL= 0 (R) go to step 6 Check TRF or wait for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4 Operation of Serial Interface WCOL: master/slave mode, set while writing to SBDR when data is transferring (transmitting or receiving) and this writing will then be ignored. WCOL function can be enabled/disabled by mask option. WCOL is set by SIO and cleared by users. Data transmission and reception are still working when the MCU enters the HALT mode. CPOL is used to select the clock polarity of CLK. It is a mask option. MLS: MSB or LSB first selection CSEN: chip select function enable/disable, CSEN=1 (R) SCS signal function is active. Master should output SCS signal before CLK signal is set and slave data transferring should be disabled (or enabled) before (after) SCS signal is received. CSEN= 0, SCS signal is not needed, SCS pin (master and slave) should be floating. CSEN has 2 options: CSEN mask option is used to enable/disable software CSEN function. If CSEN mask option is disabled, the software CSEN is always disabled. If CSEN mask option is enabled, software CSEN function can be used. SBEN= 1 (R) serial bus standby; SCS (CSEN= 1) = 1; SCS= floating (CSEN= 0); SDI= floating; SDO= 1; master CLK= output 1/0 (dependent on CPOL mask option), slave CLK= floating SBEN= 0 (R) serial bus disabled; SCS= SDI= SDO= CLK= floating TRF is set by SIO and cleared by users. When data transfer (transmission and reception) is completed, TRF is set to generate SBI (serial bus interrupt).
Slave 5. 6. 7. 8. 9.
Rev. 1.20
24
November 1, 2006
HT46RB50
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R SCS CLK SDI SDO CLKB SBCR D e fa u lt SBDR D e fa u lt D7 CKS 0 D7 u D6 M1 1 D6 u D5 M0 1 D5 u D4 SBEN 0 D4 u D3 M LS 0 D3 u D2 CSEN 0 D2 u D1 WCOL 0 D1 u D0 TRF 0 D0 u D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S B E N = C S E N = 1 a n d w r ite d a ta to S B D R ( if p u ll- h ig h e d )
N o te : "u " m e a n s u n c h a n g e d . D a ta B u s SBDR ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0 M
U X
SDO
B u ffe r SBEN
SDO
M LS M U X M U X C0C1C2 In te r n a l B a u d R a te C lo c k CLK EN a n d , s ta rt C lo c k P o la r ity a n d , s ta rt SDI
TRF AND W C O L F la g
M a s te r o r S la v e SBEN In te r n a l B u s y F la g SBEN
W r ite S B D R E n a b le /D is a b le
a n d , s ta rt EN
W r ite S B D R W r ite S B D R
SCS
M a s te r o r S la v e SBEN CSEN W C O L:setb CSEN:enab 1 . m a s te r 2 . s la v e m SBEN :enab 1.W hen S 2.W hen S T R F 1 : d a ta C P O L 1 /0 : c y S IO c le a r e d b y u s e r s le /d is a b le c h ip s e le c tio n fu n c tio m o d e 1 /0 : w ith /w ith o u t S C S B o o d e 1 /0 : w ith /w ith o u t S C S B in p le /d is a b le s e r ia l b u s ( 0 : in itia liz B E N = 0 , a ll s ta tu s fla g s s h o u ld B E N = 0 , a ll S IO r e la te d fu n c tio tr a n s m itte d o r r e c e iv e d , 0 : d a ta lo c k p o la r ity r is in g /fa llin g e d g e np u tp ut ea be np is :m in u t fu n c tio n c o n tro l fu n ll s ta tu s fla in itia liz e d in s s h o u ld tr a n s m ittin a s k o p tio n
c tio n gs) s ta y a t flo a tin g s ta te g o r s till n o t r e c e iv e d
Rev. 1.20
25
November 1, 2006
HT46RB50
Suspend Wake-Up or Remote Wake-Up If there is no signal on the signal bus for over 3ms, the HT46RB50 will go into suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT46RB50 should jump to suspend state to meet the 500mA USB suspend current spec. In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing the USBCKEN (bit3 of the UCC) to 0. The suspend current is about 400mA. The user can also further decrease the suspend current to 250mA by setting the SUSP2 (bit4 of the UCC). But if the SUSP2 is set, user should make sure not to enable the LVR OPT option, otherwise, the HT46RB50 will be reset. When the resume signal is sent out by the host, the HT46RB50 will wake-up the by USB interrupt and the Resume line (bit 3 of the USC) is set. In order to make the HT46RB50 work properly, the firmware must set the USBCKEN (bit 3 of the UCC) to 1 and clear the SUSP2 (bit4 of the UCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of the USC) is going to 0. So when the MCU is detecting the Suspend line (bit0 of USC), the Resume line should be remembered and taken into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered. The following is the timing diagram:
SUSPEND U S B R e s u m e S ig n a l
The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of the USC). Once the USB Host receive the wake-up signal from the HT46RB50, it will send a
SUSPEND M in . 1 U S B C L K RMW K
M in .2 .5 m s
U S B R e s u m e S ig n a l
U S B _ IN T
Resume signal to the device. The timing is as follow: USB Interface The HT46RB50 has 4 Endpoints (EP0~EP3). EP0~EP2 are support Interrupt transfer, EP3 is support Bulk transfer. There are 12 registers, including USC (20H), USR (21H), UCC (22H), AWR (address+remote wake-up 23H), STALL (24H), SIES (25H), MISC (26H), SETIO (27H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH) and FIFO3 (2BH) used for the USB function. The FIFO size of each FIFO is 8 byte (FIFO0), 8 byte (FIFO1), 8 byte (FIFO2) and 64 byte (FIFO3), and total of 88 bytes. URD (bit7 of the USC) is USB reset signal control function definition bit.
U S B _ IN T
Rev. 1.20
26
November 1, 2006
HT46RB50
Bit No. 0 Label SUSP R/W R Function Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indicates that the USB bus enters the suspend mode. The USB interrupt is also triggered on any changes of this bit. USB remote wake-up command. It is set by the MCU to force the USB host leaving the suspend mode. Set RMWK bit to 1 to enable remote wake-up. When this bit is set to 1, a 2ms delay for clearing this bit to 0 is needed to insure that the RMWK command is accepted by the SIE. USB reset indication. This bit is set/cleared by USB SIE. When the URST is set to 1, this indicates that a USB reset has occurred and a USB interrupt will be initialized. USB resume indication. When the USB leaves the suspend mode, this bit is set to 1 (set by SIE). This bit will appear for 20ms, waiting for the MCU to detect it. When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, MCU should set the USBCKEN and SUSP2 (in the SCC register) to enable the SIE detect function. The RESUME will be cleared while the SUSP is set to 0. When MCU detects the SUSP, the RESUME (which causes MCU to wake-up) should be remembered and token into consideration. 0/1: Turn-off/on V33O output 0:Turn-on the PLL (default mode); 1: turn-of the PLL Undefined bit, read as 0 USB reset signal control function definition 1: USB reset signal will reset the MCU 0: USB reset signal cannot reset the MCU USC (20H) Definitions The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and then selects A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF, EP2IF and EP3IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0. Bit No. 0 Label EP0IF R/W R/W Function When this bit is set to 1 (set by SIE), it indicates that the endpoint 0 is accessed and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by SIE), it indicates that the endpoint 1 is accessed and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by SIE), it indicates that the endpoint 2 is accessed and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by SIE), it indicates that the endpoint 3 is accessed and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. Undefined bit, read as 0 USR (21H) Definitions
1
RMWK
R/W
2
URST
R/W
3
RESUME
R
4 5 6 7
V33C PLL 3/4 URD
R/W R/W 3/4 R/W
1
EP1IF
R/W
2
EP2IF
R/W
3 4~7
EP3IF 3/4
R/W 3/4
Rev. 1.20
27
November 1, 2006
HT46RB50
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK) The following table defines which endpoint FIFO is selected, EPS2, EPS1 and EPS0. Bit No. Label R/W Function Accessing endpoint FIFO selection. EPS2, EPS1, EPS0: 000: Select endpoint 0 FIFO 001: Select endpoint 1 FIFO 010: Select endpoint 2 FIFO 011: Select endpoint 3 FIFO 100: Reserved for future expansion, cannot be used 101: Reserved for future expansion, cannot be used 110: Reserved for future expansion, cannot be used 111: Reserved for future expansion, cannot be used If the selected endpoints do not exist, the related functions are not available. USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. This bit is used to reduce power consumption in suspend mode. In normal mode, clear this bit to 0 (default) In HALT mode, set this bit to 1 to reduce power consumption. This bit is used to define the MCU system clock to come from either the external OSC or from PLL output 24MHz clock. 0: system clock comes from OSC 1: system clock comes from PLL output 24MHz This bit is used to specify the system clock oscillator frequency used by the MCU. If a 6MHz crystal oscillator or resonator is used, this bit should be set to 1. If a 12MHz crystal oscillator or resonator is used. this bit should be cleared to 0 (default). Undefined, read as 0 UCC (22H) Definitions The AWR register contains the current address and the remote wake-up function control bit. The initial value of the AWR is 00H. The address value extracted from the USB command is not to be loaded into this register until the SETUP stage is finished. Bit No. 0 7~1 Label WKEN AD6~AD0 R/W R/W R/W Remote wake-up enable/disable USB device address AWR (23H) Definitions The STALL register shows whether the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to 1. The STALL will be cleared by the USB reset signal. Bit No. 3~0 7~4 Label STL3~STL0 3/4 R/W R/W 3/4 Function Set by users when the related USB endpoints are stalled. They are cleared by USB reset and Setup Token event Undefined bit, read as 0 STALL (24H) Definitions Function
0~2
EPS0~EPS2
R/W
3
USBCKEN
R/W
4
SUSP2
R/W
5
fSYS (24MHz)
R/W
6
SYSCLK
R/W
7
3/4
3/4
Rev. 1.20
28
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HT46RB50
Bit No. Label R/W Function This bit is used to configure the SIE to automatically change the device address with the value stored in the AWR register. When this bit is set to 1 by firmware, the SIE will update the device address with the value stored in the AWR register after the PC host has successfully read the data from the device by IN operation. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, firmware has to clear this bit after the next valid SETUP token is received. This bit is used to indicate there are some errors occurred during the FIFO0 is accessed. This bit is set by SIE and should be cleared by firmware. This bit is used to indicate there are OUT token (except for the OUT zero length token) that have been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received. This bit is used to indicate that the current USB receiving signal from the PC host is IN token. (1=IN token; 0=Non IN token) This bit is used to indicate that the SIE has transmitted a NAK signal to the host in response to the PC host IN or OUT token. (1=NAK signal; 0=Non NAK signal) Error condition failure flag include CRC, PID, no integrate token error, CRCF will be set by hardware and the CRCF need to be cleared by firmware. Token Package active flag, low active. NAK token interrupt mask flag. If this bit is set, when the device sent a NAK token to the host, interrupt will not occur. Otherwise, when this bit is cleared, and the device sent a NAK token to the host, it will enter the interrupt sub-routine. SIES (25H) Definitions MISC register combines a command and status to control the desired endpoint FIFO action and to show the status of the desired endpoint FIFO. The MISC will be cleared by USB reset signal. Bit No. 0 Label REQUEST R/W R/W Function After selecting the desired endpoint, FIFO can be requested by setting this bit as high active. Afterwards, this bit must be set low. This indicates the direction and transition end which the MCU accesses. When set as logic 1, the MCU writes data to FIFO. Afterwards, this bit must be set to logic 0 before terminating request to indicate transition end. For reading action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1 afterwards. This indicates an MCU clear requested FIFO, even if the FIFO is not ready. After clearing the FIFO, USB interface will send force_tx_err to tell Host that data under-run if Host want to read data. Reserved bit To show that the data in FIFO is setup command. This bit will last this state until next one entering the FIFO. (1=SETCMD token; 0=Non SETCMD token) To tell that the desired FIFO is ready to work. (1=Ready to work; 0=Non ready to work) To tell that host sent a 0-sized packet to MCU. This bit must be cleared by read action to corresponding FIFO. (1=Host sent a 0-sized packet) MISC (26H) Definitions
0
ASET
R/W
1
ERR
R/W
2
OUT
R/W
3 4 5 6 7
IN NAK CRCF EOT NMI
R R R/W R R/W
1
TX
R/W
2 3~4 5 6 7
CLEAR 3/4 SETCMD READY LEN0
R/W R/W R/W R R/W
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There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing. Actions Read FIFO0 sequence Write FIFO0 sequence Check whether FIFO0 can be read or not Check whether FIFO0 can be written or not Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence to FIFO0 MISC Setting Flow and Status 00H(R)01H(R)delay 2ms, check 41H(R)read* from FIFO0 register and check not ready (01H)(R)03H(R)02H 02H(R)03H(R)delay 2ms, check 43H(R)write* to FIFO0 register and check not ready (03H)(R)01H(R)00H 00H(R)01H(R)delay 2ms, check 41H (ready) or 01H (not ready)(R)00H 02H(R)03H(R)delay 2ms, check 43H (ready) or 03H (not ready)(R)02H 00H(R)01H(R)delay 2ms, check 81H(R)read once (01H)(R)03H(R)02H 02H(R)03H(R)delay 2ms, check 03H(R)07H(R)06H(R)00H Read or Write FIFO Table Note: *: There are 2ms existing between 2 reading action or between 2 writing action
Req. Tx Req. Tx
Ready
Ready
R e a d F IF O
T im in g
W r ite F IF O
T im in g
Bit No. 0 1 2 3 4~7
Label DATATG* SETIO1** SETIO2** SETIO3** 3/4
R/W R/W R/W R/W R/W 3/4
Function To toggle this bit, all the DATA token will send a DATA0 first. Set endpoint 1 input or output pile (1/0), default input pipe (1) Set endpoint 2 input or output pile (1/0), default input pipe (1) Set endpoint 3 input or output pile (1/0), default input pipe (1) Undefined bit, read as 0
SETIO Register (27H), USB Endpoint 1~Endpoint5 Set IN/OUT Pipe Register Note: *USB definition: when the host sends a set Configuration, the Data pipe should send the DATA0 (Data toggle) first. So, when the device receives a set configuration setup command, user needs to toggle this bit so the next data will send a Data0 first. **Needs to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host from abnormally sending only an IN or OUT token and disables the endpoint. Options The following table shows all kinds of options in the microcontroller. All of the OTP options must be defined to ensure a proper functioning system. No. 1 2 3 4 5 6 Option PA0~PA7 pull-high resistor enable or disable (by bit) PB0~PB7 pull down resistor enable or disable (by bit) PC0~PC7 pull-high resistor enable or disable (by nibble) PD0~PD7 pull-high resistor enable or disable (by nibble) PE0~PE5 pull-high resistor enable or disable (by nibble) LVR enable or disable
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No. 7 8 9 10 11 12 13 14 15 16 17* Note: PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output SIO (Serial Interface) enable/disable (if SIO is enabled then PE0~PE3 I/O port will be disabled) SIO_ CPOL: Clock polarity 1/0: clock polarity rising or falling edge SIO_WCOL: Enable/disable SIO_CSEN: Enable/disable, CSEN mask option is used to enable/disable (1/0) software CSEN function WDT enable/disable WDT clock source: fSYS/4 or WDTOSC WDT timeout period: 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS CLRWDT instruction (s): 1 or 2 PA0~PA7 wake-up enable/disable (by bit) EP1~EP3 Data pipe enable: EP1, EP2, EP3 enable/disable. (Default is enable) *: The purpose of this option is to enable the endpoint that will be used, and disable the endpoint that will not be used. Option
Application Circuits
VDD USBUSB+ VSS
5W *
33W * 100kW
PA0~PA7 VDD 0 .1 m F
10kW
PB0~PB7 PC 0~PC 7 PD 0~PD 7
0 .1 m F *
RES
PE0~PE5 0 .1 m F 47pF* 33W * 47pF* USBD+ 47pF HT46RB50
1 .5 k W
5W *
0 .1 m F *
0 .1 m F * V33O 22pF OSC1 22pF OSC2 VSS USBD-
47pF
33W *
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. X1 can use 6MHz or 12MHz, X1 as close to OSC1 and OSC2 as possible Components with * are used for EMC issue 22pF capacitance are used for resonator only
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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HT46RB50
Package Information
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
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HT46RB50
28-pin SKDIP (300mil) Outline Dimensions
A 28 B 1 15 14
H C D E F G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 1375 278 125 125 16 50 3/4 295 330 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375 15
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HT46RB50
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 1000.1 13+0.5 -0.2 20.5 32.2+0.3 -0.2 38.20.2
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HT46RB50
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
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D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 320.3 160.1 1.750.1 14.20.1 2 Min. 1.5+0.25 40.1 20.1 120.1 16.20.1 2.40.1 3.20.1 0.350.05 25.5
Rev. 1.20
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November 1, 2006
HT46RB50
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
53
November 1, 2006

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